This could actually work really well based on what we’ve seen with Apple M series chips. RISC instructions are fixed size, and you can read in a batch of instructions, then look for ones that have dependencies, and run the rest in parallel. So, if you have 1,600 cores, you could process up to 1,600 instructions at a time and in best case scenario you could execute them all in parallel. In practice, you’re likely going to be executing a portion of instructions in parallel, but you still get a massive speedup basically for free. It also turns out that this design is a lot more energy efficient, so you get longer battery life for mobile devices and less energy use for server farms.
This could actually work really well based on what we’ve seen with Apple M series chips. RISC instructions are fixed size, and you can read in a batch of instructions, then look for ones that have dependencies, and run the rest in parallel. So, if you have 1,600 cores, you could process up to 1,600 instructions at a time and in best case scenario you could execute them all in parallel. In practice, you’re likely going to be executing a portion of instructions in parallel, but you still get a massive speedup basically for free. It also turns out that this design is a lot more energy efficient, so you get longer battery life for mobile devices and less energy use for server farms.